The present invention relates generally to Input/Output Controllers having Infrared Communications Controllers (IrCC) for personal computers, more particularly to a high-speed universal synchronous receiver/transmitter interface and most particularly to a loopback feature which enables a host processor or a host central processing unit (CPU) to test the transmitter and receiver of a communications device incorporated into the IrCC.
An IrCC typically comprises two main architectural units, a uniform asynchronous receiver/transmitter (UART) and a synchronous communications engine (SCE). Each unit is supported by its own unique register set.
In infrared communications controllers utilized with personal computers, the IrCC is usually incorporated into a semiconductor chip. When designing a semiconductor chip, there is considerable competition between the available resources or space on the chip and the ever increasing functions required to be accomplished by the applications with the limited physical size of the chip. Specifically, only recently on a chip of silicon roughly an inch square, Intel's Pentium chip held about three (3) million transistors, or tiny electronic switches. More recently, the number of transistors on the same inch square chip has been increased to between five (5) and six (6) million. Thus, while the number of transistors or electronic switches which can be implemented on a chip have increased, so has the number of functions that auxiliary chips, which communicate with the CPU are required to perform. Given this constant need for increased functions, chip designers are constantly looking for ways to decrease the amount of space, i.e., the number of electronic switches in a chip required to do a specific function.
Loopback is a well established technique to test the transmitter and logic therein as well as the receiver and logic therein of a communications device, such as, for example, a transceiver contained in an IrCC. Loopback obviates the need to establish a communications link between two separate communications devices in order to test just one of the devices and the need to test that device in a two step process, namely transmitter then receiver. Loopback essentially sets the communications device up for full duplex operation where its transmitter and receiver operate concurrently and establishes a link between the transmitter and the receiver by physically connecting the transmit data output to the receive data input. With the transmitter and receiver physically connected, a successful transmission can be verified by examining the received data and the status.
Previously, loopback functionality was incorporated in communications devices whose protocols, such as full duplex, required separate transmit and receive FIFOs or buffers. In such prior communications devices, loopback was performed by transmitting from a dedicated transmit buffer 20 and receiving the transmitted data into a separate dedicated receive buffer 22, such as, for example, in the Universal Asynchronous Receiver Transmitter (UART) serial port logic of Standard Microsystems Corporation's (SMC) FDC37C669 integrated circuit, as illustrated in FIG. 1.
As shown, the host CPU (not shown) would write data into the FIFO 20 and the transmitter 24 would be enabled. The transmitter 24 would then read the data in the FIFO 20 and the FIFO 20 would send data to the input 26 of the transmitter 24. The transmitter 24 would send the data from the transmitter output 28 to the receiver input 30. The receiver 32 would write the data to the FIFO 22 and the CPU would read the data which is contained in the FIFO 22 which would be sent to the CPU via the host CPU data output 34. As is clearly shown, with this prior art Loopback configuration for transceivers, two FIFO 20, 22 buffers are required.
Since these prior transceivers only transmitted and received data at the relatively slow rate of about 115 Kbps, only relatively small (about 16 bytes) capacity buffers were required to transmit and/or receive data. However, when the transmission/receive rate was increased to about 1.152 Mbps to about 4 Mbps, larger (128 Kbyte, i. e. about 128,000 bytes) buffers were required, and thus more space on the chip was required to accommodate the greatly increased data transfer rate. But, since space on the chip is limited, incorporation of two 128 k byte FIFOs or buffers in a chip, which would be required to do loopback testing as in the above method used with the UART transceiver, becomes prohibitive.
As is well known, the components of a personal computer motherboard or the main circuit board in a PC includes assorted micro chips. The motherboard typically includes a central processing unit (CPU) and other micro chips, such as, for example, input/output controllers.
With input/output controllers having transceivers, it is important that the chip having the transceiver incorporated therein be tested prior to being sent to the motherboard manufacture to ensure that the transceiver is operating properly. For example, in an input/output controller having a transceiver, the above described loopback test would typically be performed after the chip manufacturer had manufactured the chip and prior to the chip being sent to the motherboard manufacturer. Once the individual chip containing the transceiver passed the loopback test at the chip manufacturer, the individual chip would be then forwarded to the motherboard manufacturer for incorporation into a higher level product, such as, for example, a personal computer (PC) motherboard. At the PC motherboard manufacturer, after the chip containing the transceiver had been incorporated into a PC motherboard, the transceiver would again be tested by utilizing the loopback test procedure to insure that the transceiver was operating properly. At this point, the motherboard would be shipped to an end product manufacturer, such as, for example, a laptop personal computer manufacturer where, the motherboard containing the chip with the transceiver would be incorporated into a personal computer. At this point, once again the chip containing the transceiver would be tested utilizing the loopback test procedure.
Thus, there is a need for a new improved loopback transmission testing for a communications device, such as those used in a synchronous communication engine (SCE). The circuit required for the implementa-tion of loopback transmission testing should occupy as little space as possible on the chip; should perform the loopback testing utilizing only a single FIFO or buffer; should provide ease of component (chip) and board (motherboard) testability and should provide data integrity.